Apparatuses and methods consistent with example embodiments relate to a phase-locked loop (PLL) such as an all-digital PLL (ADPLL) capable of detecting whether the ADPLL is locked by using the number of toggling times of a comparison signal output by a bangbang phase frequency detector (BBPFD), a method of operating the PLL, and devices including the PLL.
A PLL is a control circuit that generates an output clock detection signal having a phase related to a phase of an input clock detection signal. The PLL is widely used in wireless communication devices, computers and other electronic devices.